Data communication channels generally include encoding of data before it passes through a communication medium, and decoding of data after it has passed through a communication medium. Data encoding and decoding are used, for example, in data storage devices for encoding data that is written on a storage medium and decoding data that is read from a storage medium. Encoding is applied in order to convert the data into a form that is compatible with the characteristics of communication medium, and can include processes such as channel detection, adding error correction codes, interleaving, turbo encoding, bandwidth limiting, amplification and many other known encoding processes. Decoding processes are generally inverse functions of the encoding processes. Encoding and decoding increases the reliability of the reproduced data.
Turbo decoding using a soft output viterbi algorithm (SOVA) is known. SOVA detectors can include one or two decoding stages and help to optimize the cost of implementation. Single stage SOVA detectors provide low latency at the cost of significantly larger areas of silicon. Dual stage SOVA detectors reduce the area of silicon, but at a cost of increased latency. In the second stage of a two stage SOVA detector, known solutions include large numbers of exclusive OR gates (XORs) or multiplexors. The large numbers of gates or multiplexors uses a large area of silicon and introduces significant delay. There is a desire to reduce the area of silicon used and to reduce the delay due to the large number of XORs or multiplexors in a second stage SOVA detector.
Embodiments of the present invention provide solutions to these and other problems, and offer other advantages over the prior art.